This design is targeted for xczu4cg board (part number: xczu4cg-sfvc784-1-e)

Zynq UltraScale+ Design Summary

Device	xczu4cg
SpeedGrade	-1
Part	xczu4cg-sfvc784-1-e
Description	Zynq UltraScale+ PS Configuration Report
Vendor	Xilinx

MIO Table View

MIO Pin	Peripheral	Signal	IO Type	Speed	Pullup	Direction	Drive Strength(mA)
MIO 0	Quad SPI Flash	sclk_out	cmos	fast	pullup	out	12
MIO 1	Quad SPI Flash	miso_mo1	cmos	fast	pullup	inout	12
MIO 2	Quad SPI Flash	mo2	cmos	fast	pullup	inout	12
MIO 3	Quad SPI Flash	mo3	cmos	fast	pullup	inout	12
MIO 4	Quad SPI Flash	mosi_mi0	cmos	fast	pullup	inout	12
MIO 5	Quad SPI Flash	n_ss_out	cmos	fast	pullup	out	12
MIO 6	SPI 1	sclk_out	cmos	fast	pullup	inout	12
MIO 7	USB0 Reset	reset	cmos	fast	pullup	out	12
MIO 8	SPI 1	n_ss_out[1]	cmos	fast	pullup	out	12
MIO 9	SPI 1	n_ss_out[0]	cmos	fast	pullup	inout	12
MIO 10	SPI 1	miso	cmos	fast	pullup	inout	12
MIO 11	SPI 1	mosi	cmos	fast	pullup	inout	12
MIO 12	GPIO0 MIO	gpio0[12]	cmos	fast	pullup	inout	12
MIO 13	SD 0	sdio0_data_out[0]	cmos	fast	pullup	inout	12
MIO 14	SD 0	sdio0_data_out[1]	cmos	fast	pullup	inout	12
MIO 15	SD 0	sdio0_data_out[2]	cmos	fast	pullup	inout	12
MIO 16	SD 0	sdio0_data_out[3]	cmos	fast	pullup	inout	12
MIO 17	SD 0	sdio0_data_out[4]	cmos	fast	pullup	inout	12
MIO 18	SD 0	sdio0_data_out[5]	cmos	fast	pullup	inout	12
MIO 19	SD 0	sdio0_data_out[6]	cmos	fast	pullup	inout	12
MIO 20	SD 0	sdio0_data_out[7]	cmos	fast	pullup	inout	12
MIO 21	SD 0	sdio0_cmd_out	cmos	fast	pullup	inout	12
MIO 22	SD 0	sdio0_clk_out	cmos	fast	pullup	out	12
MIO 23	SD 0	sdio0_bus_pow	cmos	fast	pullup	out	12
MIO 24	I2C 1	scl_out	cmos	fast	pullup	inout	12
MIO 25	I2C 1	sda_out	cmos	fast	pullup	inout	12
MIO 26	Gem 0	rgmii_tx_clk	cmos	fast	pullup	out	12
MIO 27	Gem 0	rgmii_txd[0]	cmos	fast	pullup	out	12
MIO 28	Gem 0	rgmii_txd[1]	cmos	fast	pullup	out	12
MIO 29	Gem 0	rgmii_txd[2]	cmos	fast	pullup	out	12
MIO 30	Gem 0	rgmii_txd[3]	cmos	fast	pullup	out	12
MIO 31	Gem 0	rgmii_tx_ctl	cmos	fast	pullup	out	12
MIO 32	Gem 0	rgmii_rx_clk	cmos	fast	pullup	in	12
MIO 33	Gem 0	rgmii_rxd[0]	cmos	fast	pullup	in	12
MIO 34	Gem 0	rgmii_rxd[1]	cmos	fast	pullup	in	12
MIO 35	Gem 0	rgmii_rxd[2]	cmos	fast	pullup	in	12
MIO 36	Gem 0	rgmii_rxd[3]	cmos	fast	pullup	in	12
MIO 37	Gem 0	rgmii_rx_ctl	cmos	fast	pullup	in	12
MIO 38	GPIO1 MIO	gpio1[38]	cmos	fast	pullup	inout	12
MIO 39	GPIO1 MIO	gpio1[39]	cmos	fast	pullup	inout	12
MIO 40	UART 1	txd	cmos	fast	pullup	out	12
MIO 41	UART 1	rxd	cmos	fast	pullup	in	12
MIO 42	GPIO1 MIO	gpio1[42]	cmos	fast	pullup	inout	12
MIO 43	GPIO1 MIO	gpio1[43]	cmos	fast	pullup	inout	12
MIO 44	SD 1	sdio1_wp	cmos	fast	pullup	in	12
MIO 45	SD 1	sdio1_cd_n	cmos	fast	pullup	in	12
MIO 46	SD 1	sdio1_data_out[0]	cmos	slow	pullup	inout	12
MIO 47	SD 1	sdio1_data_out[1]	cmos	slow	pullup	inout	12
MIO 48	SD 1	sdio1_data_out[2]	cmos	slow	pullup	inout	12
MIO 49	SD 1	sdio1_data_out[3]	cmos	slow	pullup	inout	12
MIO 50	SD 1	sdio1_cmd_out	cmos	slow	pullup	inout	12
MIO 51	SD 1	sdio1_clk_out	cmos	slow	pullup	out	12
MIO 52	USB 0	ulpi_clk_in	cmos	fast	pullup	in	12
MIO 53	USB 0	ulpi_dir	cmos	fast	pullup	in	12
MIO 54	USB 0	ulpi_tx_data[2]	cmos	fast	pullup	inout	12
MIO 55	USB 0	ulpi_nxt	cmos	fast	pullup	in	12
MIO 56	USB 0	ulpi_tx_data[0]	cmos	fast	pullup	inout	12
MIO 57	USB 0	ulpi_tx_data[1]	cmos	fast	pullup	inout	12
MIO 58	USB 0	ulpi_stp	cmos	fast	pullup	out	12
MIO 59	USB 0	ulpi_tx_data[3]	cmos	fast	pullup	inout	12
MIO 60	USB 0	ulpi_tx_data[4]	cmos	fast	pullup	inout	12
MIO 61	USB 0	ulpi_tx_data[5]	cmos	fast	pullup	inout	12
MIO 62	USB 0	ulpi_tx_data[6]	cmos	fast	pullup	inout	12
MIO 63	USB 0	ulpi_tx_data[7]	cmos	fast	pullup	inout	12
MIO 64	USB 1	ulpi_clk_in	cmos	fast	pullup	in	12
MIO 65	USB 1	ulpi_dir	cmos	fast	pullup	in	12
MIO 66	USB 1	ulpi_tx_data[2]	cmos	fast	pullup	inout	12
MIO 67	USB 1	ulpi_nxt	cmos	fast	pullup	in	12
MIO 68	USB 1	ulpi_tx_data[0]	cmos	fast	pullup	inout	12
MIO 69	USB 1	ulpi_tx_data[1]	cmos	fast	pullup	inout	12
MIO 70	USB 1	ulpi_stp	cmos	fast	pullup	out	12
MIO 71	USB 1	ulpi_tx_data[3]	cmos	fast	pullup	inout	12
MIO 72	USB 1	ulpi_tx_data[4]	cmos	fast	pullup	inout	12
MIO 73	USB 1	ulpi_tx_data[5]	cmos	fast	pullup	inout	12
MIO 74	USB 1	ulpi_tx_data[6]	cmos	fast	pullup	inout	12
MIO 75	USB 1	ulpi_tx_data[7]	cmos	fast	pullup	inout	12
MIO 76	CAN 1	phy_tx	cmos	fast	pullup	out	12
MIO 77	CAN 1	phy_rx	cmos	fast	pullup	in	12

PS Clocks information

PSS REF CLK : 33.333

Name	Source	Input Frequency (MHz)
APLL	PSS_REF_CLK	2133.312
DPLL	PSS_REF_CLK	2399.976
VPLL	PSS_REF_CLK	2999.970
RPLL	PSS_REF_CLK	1599.984
IOPLL	PSS_REF_CLK	2999.970

Peripheral	Requested Frequency (MHz)	Source	Actual Frequency (MHz)
GEM0 freq (MHz)	125	IOPLL	124.998749
GEM2 freq (MHz)	125	IOPLL	124.998749
USB0 freq (MHz)	250	IOPLL	249.997498
USB1 freq (MHz)	250	IOPLL	249.997498
QSPI freq (MHz)	125	IOPLL	124.998749
SDIO0 freq (MHz)	200	IOPLL	187.498123
SDIO1 freq (MHz)	50	IOPLL	49.999500
UART0 freq (MHz)	100	IOPLL	99.999001
UART1 freq (MHz)	100	IOPLL	99.999001
I2C0 freq (MHz)	100	IOPLL	99.999001
I2C1 freq (MHz)	100	IOPLL	99.999001
SPI1 freq (MHz)	200	RPLL	199.998001
CAN0 freq (MHz)	100	IOPLL	99.999001
CAN1 freq (MHz)	100	IOPLL	99.999001
CPU_R5 freq (MHz)	500	IOPLL	499.994995
IOU_SWITCH freq (MHz)	267	RPLL	266.664001
LPD_SWITCH freq (MHz)	500	IOPLL	499.994995
LPD_LSBUS freq (MHz)	100	IOPLL	99.999001
GEM_TSU freq (MHz)	250	IOPLL	249.997498
TIMESTAMP freq (MHz)	100	PSS_REF_CLK	33.333000
PSU__CRL_APB__USB3_REF_CTRL__freqmhz	20	IOPLL	19.999800
PCAP freq (MHz)	200	IOPLL	187.498123
DBG_LPD freq (MHz)	250	IOPLL	249.997498
ADMA freq (MHz)	500	IOPLL	499.994995
PL0 freq (MHz)	100	RPLL	99.999001
AMS freq (MHz)	50	IOPLL	49.999500
ACPU freq (MHz)	1200	APLL	1066.656006
DBG FPD freq (MHz)	250	IOPLL	249.997498
DP VIDEO freq (MHz)	300	DPLL	299.997009
DP AUDIO freq (MHz)	25	VPLL	24.999750
DP STC freq (MHz)	27	DPLL	26.666401
DDR_CTRL freq MHz)	600.000	DPLL	599.994019
GDMA freq (MHz)	600	DPLL	599.994019
DPDMA freq (MHz)	600	DPLL	599.994019
TOPSW_MAIN freq (MHz)	533.333	APLL	533.328003
TOPSW_LSBUS freq (MHz)	100	IOPLL	99.999001
DBG TSTMP freq (MHz)	250	IOPLL	249.997498

DDR Memory information

Parameter name	Value	Description
ENABLE	1	Enable the PS DDR Controller
DDR Interface freq (MHz)	1200	--
MEMORY TYPE	DDR 4	Type of memory interface
DM DBI	Components
BUS WIDTH	64 Bit	Data width of DDR interface, not including ECC data width
ECC	Disabled	Enables error correction code support
SPEED BIN	DDR4_2400P	Speed Bin
CL	16	Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL	12	CAS write latency setting in memory clock cycles
DDR AL	0	Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD	16	tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP	16	Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC	45.32	Row cycle time (ns)
T RAS MIN	32	Minimum number of memory clock cycles required between an Active and Precharge command
T FAW	30.0	Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH	16 Bits	Width of individual DRAM components
DEVICE CAPACITY	4096 MBits	Storage capacity of individual DRAM components
BG ADDR COUNT	1	Number of bank group address pins
RANK ADDR COUNT	0	Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT	2	Number of bank address pins
ROW ADDR COUNT	15	Number of row address pins
COL ADDR COUNT	10	Number of column address bits
C_DDR_RAM_HIGHADDR	0x7FFFFFFF	--

GT lanes information

Protocol	GT lane#	Ref Clk Sel	Ref freq (MHz)
DP	GT Lane0	Ref Clk1	27
Gem2	GT Lane2	Ref Clk2	125
USB1	GT Lane3	Ref Clk0	26